Senior Lead Synthesis Engineer

About the role

We are looking for a Senior Lead Synthesis Engineer to drive physical synthesis and timing closure for advanced hardware designs. The role involves collaborating with design, DFT and PD teams to deliver high‑quality netlists and meet performance targets.

Key responsibilities

• Develop and optimize physical synthesis and synthesis methodologies using industry‑standard tools.
• Create and manage timing constraints, perform STA, and achieve timing closure across multi‑clock domain designs.
• Perform MCMM synthesis, low‑power implementation using UPF, and power‑optimization techniques such as clock gating.
• Write and maintain scripts in Perl, Python, and TCL to automate flows.
• Collaborate with design, DFT and PD teams for netlist delivery and constraint validation.
• Handle engineering change orders (ECOs) and conduct formal verification to ensure design quality.

Required profile

• Bachelor’s degree in Computer Science, Electrical/Electronics Engineering or related field with 3+ years of hardware engineering experience (or higher degree with reduced experience as specified).
• 5+ years of experience in physical synthesis, timing closure, and low‑power design.
• Strong understanding of MCMM synthesis, multi‑clock domain designs, and UPF.

Required skills

• Physical synthesis and synthesis tools
• Static timing analysis (STA) and timing constraint creation
• MCMM synthesis and optimization
• Low‑power design implementation using UPF
• Scripting in Perl, Python, TCL
• Clock gating and other power‑optimization techniques
• ECO handling and formal verification