Senior Staff ASIC Design Engineer

About the role

Join Axiado to lead the design and integration of cutting‑edge System‑on‑Chip (SoC) solutions, driving micro‑architecture, RTL development, and chip validation from concept through production.

Key responsibilities

• Develop the design and implementation/integration of SoCs.
• Perform micro‑architecture design, RTL coding, synthesis, timing closure, and documentation of various RTL blocks.
• Support prototyping, test program development, chip validation, and chip life‑cycle until production maturity.
• Collaborate with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout ASIC development.

Required profile

• 12+ years of experience in RTL logic design, verification, synthesis, and timing optimization.
• Proficient in writing clear micro‑architecture specifications and efficient Verilog RTL code.
• Experience with interface protocols such as PCIe, USB, Ethernet, DDR/LPDDR4/5, I2C/I3C, eSPI, and SPI.
• Experience with FPGA emulation platforms (HAPS, Veloce) and at least one complete tape‑out cycle.

Required skills

• Verilog RTL coding.
• Scripting in Perl and Python.
• Assertions, coverage analysis, RTL synthesis, and timing closure.
• Repository management (Bitbucket, Jenkins) and bug tracking (JIRA).