Senior Lead Design Engineer
nxp · Bangalore
Job description
About the role
NXP's MCU/MPU Engineering team seeks a Senior Lead Design Engineer to drive SoC debug, micro‑architecture, and integration from specification through tape‑out and post‑silicon phases.
Key responsibilities
- Lead SOC debug, micro‑architecture definition and integration from initial specification to tape‑out and beyond.
- Define and propagate best‑in‑class SoC design methodologies across multiple business lines.
- Sign‑off RTL, timing constraints, CDC, RDC and collaborate with verification, DFT, synthesis and other functions to achieve production‑quality silicon.
- Document SOC design and micro‑architecture for cross‑functional use.
- Provide debug support for silicon issues in the post‑silicon phase.
Required profile
- 5‑10 years of experience in IP/SoC design with successful production chip deliveries.
- Hands‑on expertise in ASIC design flow from specification to RTL sign‑off.
- Strong knowledge of digital design, Verilog coding and integration of debug logic.
- Experience with chip assembly, IP integration, CDC/RDC/Lint and synthesis tools.
- Self‑motivated team player with excellent written and verbal communication.
Required skills
- ARM Cortex‑M/A/R processor‑based SoC debug infrastructure (CoreSight, ETM, STM, DAP, CTI, JTAG, SWD, Trace32).
- Verilog RTL coding and digital design.
- Micro‑architecture definition, clocking, reset, safety and security architectures.
- Familiarity with bus protocols (AXI, ACE, APB, ATB) and peripherals such as PCIe, USB, DDR.
- Knowledge of serial interfaces, multimedia and external bus interfaces.
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Published 7 hours ago
Expires 1 month from now
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nxp
Bangalore