Senior PCIe CXL RTL Design Engineer

About the role

Rambus is seeking a senior engineer to join its PCIe and CXL IP design team. The role involves contributing to architecture and micro‑architecture of next‑generation PCIe/CXL/AMBA controller IP, implementing designs in SystemVerilog, and prototyping on cutting‑edge FPGAs.

Key responsibilities

• Define and develop architecture and micro‑architecture for PCIe, CXL and AMBA controller IP.
• Write RTL code in Verilog/SystemVerilog.
• Collaborate with verification teams to ensure functional correctness.
• Prototype IP on advanced FPGA platforms.
• Work closely with local and international engineering teams.

Required profile

• Master’s degree or PhD in Electrical Engineering, Computer Engineering or a related field.
• 7+ years of RTL design experience.
• Strong English communication skills.
• Willingness to work in a multicultural, multinational environment.

Required skills

• Verilog
• SystemVerilog
• PCIe
• CXL
• AMBA protocols
• FPGA prototyping

What we offer

• Hybrid work model (average three days onsite, two days remote).
• Comprehensive health insurance.
• Employee Stock Purchase Plan.
• Extra vacation day each quarter.
• Regular team lunches and breakfasts.
• Competitive compensation including base salary, bonus and equity.