Principal PCIe CXL RTL Design Engineer

About the role

Rambus is seeking a motivated Principal PCIe CXL RTL Design Engineer to join its high‑performance IP design team. You will contribute to the architecture and micro‑architecture of next‑generation PCIe, CXL and AMBA controller IPs and prototype them on cutting‑edge FPGAs.

Key responsibilities

• Define and develop the architecture and micro‑architecture of PCIe, CXL and AMBA controller IP.
• Implement designs in SystemVerilog and Verilog.
• Collaborate with verification engineers to ensure functional correctness.
• Prototype IP blocks on advanced FPGA platforms.
• Work closely with both local and international multi‑disciplinary teams.

Required profile

• Master's degree or PhD in Electrical Engineering, Computer Engineering or a related field.
• 5+ years of professional RTL design experience.
• Strong English communication skills and ability to work in a multicultural environment.

Required skills

• Verilog
• SystemVerilog
• PCIe
• CXL
• AMBA protocols
• FPGA prototyping

What we offer

• Hybrid work model (average three days onsite, two days remote).
• Comprehensive health insurance.
• Employee Stock Purchase Plan.
• Extra vacation day each quarter.
• Regular team lunches and breakfasts.