Synthesis & Front-End Implementation Engineer

About the role

We are seeking a highly motivated Synthesis & Front-End Implementation Engineer to join our dynamic team. In this role you will translate RTL designs into optimized gate-level netlists while meeting performance, power and area targets for complex IP blocks.

Key responsibilities

• Perform synthesis of RTL designs for digital blocks and subsystems using hierarchical methodologies.
• Develop and apply timing constraints (SDC) to achieve target frequencies and optimize performance.
• Conduct static timing analysis, identify critical paths and work with design teams to close timing.
• Execute formal verification (LEC) to ensure functional equivalence between RTL and synthesized netlists.
• Analyze and optimize power consumption at the front-end stage using power analysis tools.
• Estimate and optimize area to meet chip size requirements.
• Collaborate with RTL designers, DFT and physical design engineers for seamless hand-off.
• Create and maintain automation scripts (Tcl, Python, Perl) for synthesis flows.
• Evaluate and integrate new CAD tools and methodologies.

Required profile

• Bachelor’s or Master’s degree in Electrical or Computer Engineering or related field.
• 5+ years of experience in digital ASIC/SoC design focusing on synthesis and front-end implementation.
• Strong problem-solving skills, attention to detail and ability to work across multiple time zones.

Required skills

• Synopsys Design Compiler or Fusion Compiler.
• Synopsys PrimeTime for static timing analysis.
• Formal verification tools such as Synopsys Formality or Cadence Conformal.
• Proficiency in Verilog/SystemVerilog.
• Scripting in Tcl, Python and Perl.
• Understanding of UPF, low-power design techniques and power analysis.