Senior Synthesis & Front-End Implementation Engineer

About the role

We are looking for a highly motivated Senior Synthesis & Front-End Implementation Engineer to join our AI NPU team. You will translate RTL designs into optimized gate-level netlists, ensuring performance, power and area targets are met for complex IP blocks.

Key responsibilities

• Perform logical and physical synthesis of RTL for digital blocks and subsystems, using hierarchical methodologies.
• Develop and apply timing constraints (SDC) to achieve target frequencies and drive timing closure.
• Run static timing analysis, identify critical paths and collaborate with design teams for closure.
• Execute formal equivalence checking (LEC) between RTL and synthesized netlists.
• Analyze and optimize front-end power consumption using power analysis tools.
• Estimate and optimize area to meet aggressive PPA goals.
• Collaborate with RTL, DFT and physical design engineers for seamless hand-off.
• Create and maintain automation scripts (Tcl, Python, Perl) for synthesis flows.
• Evaluate and integrate new CAD tools and methodologies.
• Document constraints, methodologies and analysis results.

Required profile

• Bachelor’s or Master’s degree in VLSI, Electronics Engineering or related field.
• 5+ years of ASIC/SoC digital design experience focused on synthesis and front-end implementation.
• Strong problem-solving skills, attention to detail and ability to work across multiple time zones.

Required skills

• Synopsys Design Compiler / Fusion Compiler
• Cadence Genus
• Synopsys PrimeTime or Cadence Tempus for STA
• Synopsys Formality or Cadence Conformal for LEC
• Verilog / SystemVerilog
• Tcl, Python, Perl scripting
• UPF and low-power design techniques