Senior Physical Design Engineer

About the role

We are looking for a high-energy, technically curious Physical Design Engineer to join our advanced silicon team. This isn’t a role for someone who wants to just “push buttons” on a vendor flow. We need a driver—someone with 4–6 years of experience who has lived through the trenches of quality tape‑outs and is hungry to take full ownership of complex partitions.

Key responsibilities

• Lead the physical implementation of complex blocks from synthesis and floor‑planning through to CTS, routing, and sign‑off.
• Perform deep‑dive analysis on timing paths, power profiles, and congestion to derive custom optimization strategies.
• Use Tcl and Python to automate repetitive tasks, build custom analysis scripts, and enhance the efficiency of the physical design environment.
• Take a partition from “dirty” RTL to a clean GDSII, resolving complex DRC/LVS, IR drop, and timing violations with minimal supervision.
• Work closely with RTL and DFT teams to “left‑shift” physical constraints, ensuring the design is optimized for routing and timing from the start.

Required profile

• Coachable with a high “workability” quotient, able to execute complex instructions and flag inefficient processes.
• Detective mindset: dig into logs and data to find root causes when tools fail or timing won’t close.
• Driven & independent with a “get it done” attitude and ability to unblock yourself through research and experimentation.
• Curious about tool psychology and able to drive it as an expert driver.

Required skills

• 4–7 years in Physical Design with at least 2–3 successful tape‑outs.
• Hands‑on experience with Cadence Innovus and Cadence Tempus.
• Proficiency in Tcl for tool control.
• Proficiency in Python for data parsing and flow automation.
• Strong debugging skills in STA, EM/IR analysis, and physical verification (DRC/LVS/ERC).