Senior Memory Design Engineer

About the role

The Senior Memory Design Engineer will lead the design and development of high‑performance SRAM and register‑file compilers across advanced technology nodes (28 nm to 5 FF). You will be responsible for creating and optimizing critical circuit blocks, ensuring yield and performance targets are met.

Key responsibilities

• Design and simulate core memory components such as bit‑cells, word‑line decoders, sense amplifiers, column decoders and control logic.
• Develop and run critical‑path and margin‑characterization flows, including statistical analysis of bit‑cell and sense‑amplifier performance.
• Perform sign‑off tuning, margin analysis and yield optimization for complete memory compilers.
• Execute logic simulations and detailed timing analysis of high‑speed memory paths.
• Conduct signal‑integrity (EM) and power‑integrity (IR‑drop) analyses and incorporate findings into the design.
• Debug silicon failures, analyze root causes and implement corrective actions.

Required profile

• Master’s degree with ≥ 4 years or Bachelor’s degree with ≥ 5 years of experience in CMOS circuit design.
• Proven experience designing and delivering memory compilers in sub‑nanometer technologies.
• Deep knowledge of split‑rail, power‑gating architectures and low‑power design techniques.
• Hands‑on silicon debug and failure analysis expertise.

Required skills

• High‑speed/low‑power CMOS circuit design, clocking schemes, static and dynamic logic.
• Memory compiler development for SRAM and register‑file blocks.
• Cadence and Mentor schematic/layout editors.
• Circuit simulation tools: HSPICE, HSIM, XA, FinSim, XARA, nWave, waveform viewers.
• Scripting in Skill, Perl and Python.
• Understanding of layout challenges in sub‑nanometer regimes and memory DFT concepts.