Senior Engineer RTL Design
arrow · Ahmedabad
Job description
About the role
The Senior Engineer RTL Design will lead RTL development for ASIC and FPGA projects, ensuring successful completion of front‑end design flow from specification to RTL and netlist.
Key responsibilities
- Develop RTL for ASIC/FPGA designs and manage the full front‑end flow.
- Perform RTL coding, lint checks, and clock domain crossing (CDC) analysis.
- Support and sustain existing designs.
- Collaborate with hardware board design engineers on system‑level and board‑level block diagrams and validation using company‑specified tools.
Required profile
- 5–7 years of relevant experience or equivalent with a 4‑year degree (or 3 years with an advanced degree).
- Ability to work independently with minimal guidance and provide informal mentorship to junior staff.
- Strong problem‑solving skills and experience contributing to process improvements.
Required skills
- RTL development for ASIC and FPGA.
- RTL coding, lint, and CDC verification.
- Hardware board design collaboration.
Questions fréquentes
Why are you reporting this job?
Explore further
Salaries, guides and searches in India.
Salaries by job title
Apply in 30 seconds
Enter your email to apply. An account will be created automatically.
By continuing, you accept our terms of use.
Already have an account? Login
A question about this job?
Ask it here: you will get the full job summary by e-mail, right away.
Published 2 hours ago
Expires 1 month from now
4 views · 0 interested
Boost your chances
Upload your CV — we will match you with relevant openings.
Analyzing your CV...
arrow
Ahmedabad