Physical Design Engineer (2-4 yrs experience)

About the role

EnCharge AI is seeking a high‑caliber Physical Design Engineer to join its fast‑paced startup team in Bangalore. The role offers end‑to‑end ownership of RTL‑to‑GDSII implementation for next‑generation AI‑driven silicon, targeting advanced nodes of 3 nm and below.

Key responsibilities

• Drive RTL‑to‑GDSII flow including floorplanning, placement, CTS, routing and physical verification (LVS/DRC/ERC).
• Close performance targets by optimizing power, performance and area (PPA) on 3 nm or smaller processes.
• Perform comprehensive static timing analysis, signal‑integrity and crosstalk checks, including CPPR optimization.
• Conduct power‑integrity studies such as IR‑drop (static and dynamic) and electromigration analysis.
• Develop AI/ML‑based automation scripts to accelerate the physical design flow.

Required profile

• B.Tech/M.Tech in Electrical/Electronics Engineering from a top‑tier university.
• 2–4 years of hands‑on physical design experience in the semiconductor industry.
• Expert‑level proficiency with industry‑standard tools, preferably Cadence Innovus.
• Strong knowledge of multi‑corner multi‑mode (MCMM) closure, low‑power techniques (UPF/CPF) and physical verification.
• Proven “go‑getter” attitude with the ability to own blocks under tight deadlines.

Required skills

• Cadence Innovus (or equivalent place‑and‑route tool).
• Python and Tcl scripting for EDA automation.
• AI/ML model integration for design flow optimization.
• Static timing analysis, CPPR, signal‑integrity and crosstalk analysis.
• Power‑integrity analysis including IR‑drop and electromigration checks.
• PPA optimization and MCMM closure techniques.