ASIC Verification Engineer (EEJ)

About the role

We are looking for an experienced ASIC Verification Engineer to join Bosch’s Bengaluru development centre. The role focuses on verifying automotive ASICs, SoCs and related IP blocks using metric‑driven and formal verification techniques.

Key responsibilities

• Develop and maintain verification plans for ASICs, subsystems and IPs.
• Create verification environments and VIP from scratch.
• Apply constrained‑random verification, functional coverage and metric‑driven verification methodologies.
• Integrate and use verification IP (VIP) and measure regression results.
• Collaborate with EDA partners to continuously improve verification flows, tools and processes.
• Track and report bugs using configuration‑management and bug‑tracking tools.

Required profile

• 5‑10 years of digital RTL verification experience using SystemVerilog and UVM.
• Hands‑on experience with Cadence, Synopsys or Mentor verification tools.
• Experience with ASIC/SoC tape‑outs and AMBA protocol verification.
• Degree in Electronics, Communication or related field (B.E./B.Tech, M.E./M.Tech).

Required skills

• SystemVerilog, UVM, OVMS
• Cadence, Synopsys, Mentor verification tools
• Perl, TCL scripting
• AMBA protocols, ARM‑based subsystem verification
• VHDL/Verilog, SPECMAN (optional)
• Metric‑driven verification, formal verification (optional)