VLSI Engineer (Level 3) – Verification & Development

About the role

The VLSI Engineer (Level 3) will develop and verify complex VLSI IP blocks for our clients. You will work on architecture definition, layout, implementation, and provide ongoing support throughout the product lifecycle.

Key responsibilities

• Define functionality, architecture, and layout for VLSI modules.
• Create verification environments using Universal Verification Methodology (UVM) and develop test benches.
• Write, review, and debug RTL and verification code.
• Execute test cases, perform functional coverage analysis, and document results in SharePoint or JIRA.
• Conduct regression testing and ensure IP meets quality standards.
• Troubleshoot, debug, and upgrade existing designs with minimal latency.
• Generate scripts to automate verification tasks.
• Prepare weekly and monthly status reports, maintain design documentation, and manage time‑sheets.

Required profile

• 3–5 years of experience in VLSI design and verification.
• Strong understanding of hardware description languages and verification methodologies.
• Ability to work independently and collaborate with cross‑functional teams.

Required skills

• VLSI Board Design
• Universal Verification Methodology (UVM)
• JIRA
• SharePoint

What we offer

• Opportunity to work on cutting‑edge VLSI projects for global clients.
• Professional development and skill‑advancement programs.
• Collaborative environment within a leading digital transformation company.