Staff/Senior Staff Physical Design Floorplan & PDN Lead

About the role

EnCharge AI is seeking a Staff or Senior Staff Physical Design Engineer to lead chip‑level floorplanning and Power Delivery Network (PDN) design for large‑scale SoCs. The role bridges RTL/Systems and final GDSII, influencing power, performance and area across the product.

Key responsibilities

• Lead architectural floorplanning, including macro placement, pin assignment and partition definition for multi‑million gate designs.
• Design and implement complex PDNs, defining metal stack usage and grid density while minimizing routing congestion.
• Perform exhaustive IR‑drop (static/dynamic) and electromigration analysis, diagnosing root causes and proposing fixes.
• Collaborate with RTL and architecture teams to make PPA trade‑offs, influencing bus widths, pipeline stages and memory configurations.

Required profile

• 10–14 years of physical design experience with multiple tape‑outs at advanced nodes (7nm, 5nm or 3nm).
• B.Tech/M.Tech in Electrical/Electronic Engineering or equivalent.
• Critical thinker with design‑thinking mindset and ability to influence cross‑functional stakeholders.

Required skills

• Industry‑standard floorplanning tools such as Innovus or IC Compiler II.
• Strong PDN design expertise, including multi‑voltage domains and thermal‑aware modeling.
• IR‑drop and electromigration analysis capabilities.
• Advanced scripting in Tcl, Python or Perl for automation.