Staff Engineer: STA Methodology & Sign-off Lead

About the role

EnCharge AI is looking for a high‑caliber Staff or Senior Staff Engineer to architect and lead the SOC Static Timing Analysis (STA) methodology. You will define frameworks and flows that bridge architecture, CAD, RTL, and physical design to enable predictable, high‑performance tape‑out for large‑scale SOCs.

Key responsibilities

• Define and own full‑chip SOC timing sign‑off criteria, including Multi‑Mode Multi‑Corner (MMMC) definitions, derate strategies, and operating condition mapping.
• Architect, deploy, and maintain advanced STA and ECO flows, proactively identifying structural timing issues early in RTL/synthesis.
• Evaluate, qualify, and deploy new EDA tool features (focus on Cadence Tempus) to improve QoR and runtime efficiency.
• Develop scalable automation utilities (Tcl, Python, Perl) for constraint (SDC) management and cross‑domain timing audits.
• Partner with Physical Design to define optimal clock‑tree synthesis (CTS) methodologies and floor‑planning guidelines.
• Guide DFT and RTL teams on methodology to resolve bottlenecks such as NoC timing and complex CDC paths.

Required profile

• 8–11 years of hands‑on VLSI design experience with a focus on STA methodology and sign‑off at advanced nodes (7nm, 5nm or below).
• B.Tech/M.Tech in Electrical/Electronics Engineering or a related field.
• Proven ability to architect broad flow solutions, debug systemic tool bottlenecks, and influence cross‑functional teams.

Required skills

• Static Timing Analysis (STA) methodology and sign‑off.
• Cadence Tempus.
• Multi‑Mode Multi‑Corner (MMMC) flow architecture.
• Tcl, Python, Perl scripting for automation.
• SDC constraint management.
• Clock‑tree synthesis (CTS) and NoC timing knowledge.