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Senior UCIe Verification Engineer

edgecortix · Hyderabad Knowledge City

New
Senior 🇬🇧 English
SystemVerilog UVM SystemVerilog Assertions UCIe AXI4 PCIe CXL Python Perl Tcl Git

Job description

About the role

Edgecortix is seeking a Senior UCIe Verification Engineer to lead verification of high‑speed chiplet interconnect IP and SoC subsystems. The role involves building reusable UVM environments, ensuring protocol compliance, and driving verification closure for tape‑out ready designs.

Key responsibilities

  • Develop and execute comprehensive verification plans for UCIe IP, subsystems, and SoC integration.
  • Build reusable SystemVerilog/UVM verification environments from scratch.
  • Create constrained‑random and directed test scenarios covering link initialization, sideband communication, data transfer, power management, error detection, and reset sequences.
  • Verify interoperability with upper‑layer protocols such as PCIe, CXL, or streaming interfaces.
  • Implement UVM agents, scoreboards, monitors, protocol checkers, and functional coverage models.
  • Write and debug SystemVerilog Assertions (SVA) for protocol compliance.
  • Perform coverage analysis, drive functional and code coverage closure, and support gate‑level simulations.
  • Collaborate with architecture, RTL, DFT, firmware, physical design, and validation teams throughout the product cycle.

Required profile

  • 6–12 years of functional verification experience using SystemVerilog and UVM.
  • Proven ability to develop complete UVM verification environments from scratch.
  • Strong understanding of UCIe architecture and high‑speed serial/chiplet interconnect protocols.
  • Hands‑on experience with AXI4, clock‑domain and reset‑domain crossings, and protocol compliance verification.
  • Experience in at least one successful SoC tape‑out and integration of UCIe subsystems.
  • Familiarity with emulator‑based verification, formal verification, and CI/CD tools (Jenkins, GitLab CI).

Required skills

  • SystemVerilog
  • UVM
  • SystemVerilog Assertions (SVA)
  • UCIe protocol
  • AXI4
  • PCIe / CXL interfaces
  • Python, Perl, Tcl scripting
  • Git version control

What we offer

  • Highly competitive salary and stock options
  • Flex work time
  • Top‑tier employee benefits

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Published 12 hours ago

Expires 1 month from now

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edgecortix

Hyderabad Knowledge City