Senior Synthesis & Front-End Implementation Engineer

About the role

We are looking for a highly motivated Senior Synthesis & Front‑End Implementation Engineer to join our AI NPU team. You will translate RTL designs into optimized gate‑level netlists while meeting performance, power and area targets for complex IP blocks.

Key responsibilities

• Perform logical and physical synthesis of RTL for digital blocks and subsystems, using hierarchical methodologies.
• Develop and apply robust timing constraints (SDC) and conduct static timing analysis to achieve target frequencies.
• Execute formal equivalence checking (LEC) to verify RTL and netlist functionality.
• Analyze and optimize power consumption and area to meet aggressive PPA goals.
• Collaborate with RTL designers, DFT and physical design engineers for seamless hand‑off.
• Create and maintain automation scripts (Tcl, Python, Perl) for synthesis flows.
• Evaluate and integrate new CAD tools and methodologies.
• Document constraints, methodologies and analysis results.

Required profile

• Bachelor's or Master's degree in VLSI, Electronics Engineering or related field.
• 5+ years of ASIC/SoC digital design experience focused on synthesis and front‑end implementation.
• Strong problem‑solving skills and ability to work across multiple time zones.

Required skills

• Synopsys Design Compiler / Fusion Compiler or Cadence Genus.
• Synopsys PrimeTime or Cadence Tempus for STA.
• Synopsys Formality or Cadence Conformal for formal verification.
• Verilog / SystemVerilog.
• Tcl, Python, Perl scripting.
• UPF, low‑power design techniques and power analysis.
• Knowledge of DFT principles (optional).