Senior Staff / Principal SOC Floorplan Lead

About the role

We are seeking a highly skilled and hands‑on SoC Floorplan Lead to own the physical foundation of our next‑generation AI and Data Center SoCs. In this critical role you will bridge architecture, logic design, and physical design, working closely with Chip Architects and RTL Leads to achieve best‑in‑class Power, Performance, and Area (PPA). The position is based in Bangalore and offers the chance to shape cutting‑edge silicon in a fast‑moving start‑up environment.

Key responsibilities

• Own the SoC‑level floorplan from concept to tape‑out for high‑performance AI/Data Center chips on advanced nodes (5nm, 3nm or below).
• Partner with Architecture and RTL teams to provide early physical feasibility feedback, drive block partitioning, shape optimization, and data‑flow planning.
• Lead bump planning, IO ring definition, and co‑design with packaging teams for flip‑chip/advanced packaging constraints.
• Manage placement and custom routing for critical analog/mixed‑signal IPs, high‑speed SerDes (PCIe, Ethernet, Memory), PLLs, and clock distribution.
• Design and analyze the top‑level power delivery network to ensure robust power for high‑current AI workloads.
• Develop scalable floorplanning workflows and scripts (Tcl, Python) for a lean start‑up team.

Required profile

• 12+ years of hands‑on physical design floorplanning experience, with at least 3 years as primary owner of SoC‑level floorplans.
• Proven track record of tape‑out for large, complex Data Center, Networking, or AI/ML chips.
• Start‑up mentality: self‑motivated, comfortable with ambiguity, and takes extreme ownership.
• Deep understanding of how RTL and architectural decisions impact physical PPA.
• BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field.

Required skills

• Cadence Innovus
• Tcl scripting
• Python scripting
• Perl scripting
• Makefile automation
• Bump planning and flip‑chip package co‑optimization
• Analog/mixed‑signal IP integration and custom routing
• Power delivery network (PDN) design and IR‑drop analysis

What we offer

• Impact: Build ground‑up architecture and see your ideas taped out in cutting‑edge silicon.
• Equity: Competitive start‑up equity packages.
• Culture: Flat, collaborative, bureaucracy‑free environment with top‑tier industry veterans.