Senior RTL Design Engineer – SOC Integration

About the role

AMD is seeking a senior RTL design engineer to join its Silicon Design team. The role focuses on SOC integration, ASIC design verification, and delivering high‑quality, industry‑leading technologies for next‑generation computing platforms.

Key responsibilities

• Drive and improve AMD’s ASIC design flow and verification processes for sub‑20nm technology nodes.
• Develop and verify RTL in Verilog/SystemVerilog, perform timing analysis, and ensure low‑power digital design compliance.
• Collaborate with globally distributed engineering teams to integrate modern SOC tools and resolve cross‑functional issues.

Required profile

• Passion for complex processor architectures and digital design verification.
• Strong analytical, problem‑solving, and communication skills, with experience working in geographically dispersed teams.

Required skills

• ASIC design flow experience in sub‑20nm nodes.
• RTL design in Verilog/SystemVerilog.
• Circuit timing/STA using PrimeTime or equivalent.
• Low‑power digital design and analysis.
• Modern SOC tools: Spyglass, Questa CDC, Cadence Conformal, VCS simulation.
• Programming/scripting: C, TCL, Perl, Python.
• Version control: Perforce, ICManage, Git.