Senior IP DV Engineer – NOC IP

About the role

NVIDIA is looking for a Senior IP DV Engineer to lead verification of next‑generation memory subsystem units for GPUs and SoCs. You will work on cutting‑edge AI and graphics products, ensuring the correctness of complex ASIC designs.

Key responsibilities

• Verify ASIC design, architecture and micro‑architecture of memory sub‑systems using advanced verification methodologies.
• Define verification scope, develop test plans, and build verification infrastructure.
• Create reusable bus functional models, monitors, checkers and scoreboards following coverage‑driven approaches.
• Apply SystemVerilog/UVM and other high‑level verification languages to achieve functional coverage closure.
• Collaborate with architects, designers, and pre‑/post‑silicon verification teams.

Required profile

• B.Tech/M.Tech or equivalent engineering degree.
• 5+ years of experience in verification of complex IPs or subsystems.
• Strong background in random stimulus, functional coverage and assertion‑based verification.
• Proficiency in Verilog and knowledge of SystemVerilog, UVM or VMM.

Required skills

• Verilog
• SystemVerilog
• UVM (or VMM) methodology
• Coverage‑driven verification
• Assertion‑based verification
• Scripting for automation and debugging

What we offer

• Competitive salary and generous benefits package.
• Opportunity to work on industry‑leading GPU and AI technologies.
• Inclusive, diverse, and innovative work environment.