Senior Engineer - Memory Circuit Design Verification

About the role

Micron Technology is seeking a Senior Engineer to lead memory circuit design verification. The role focuses on fast‑spice based verification of DRAM critical timings and full‑chip analog simulations across process, voltage, and temperature corners.

Key responsibilities

• Perform fastspice (Primesim/FineSim/SpectreFx) verification to sign‑off DRAM critical timings.
• Guide and set direction for verification efforts within assigned projects.
• Execute full‑chip analog SPICE simulations and analysis across PVTs and speed grades.
• Provide verification support by simulating, analyzing, and debugging pre‑silicon full‑chip designs.
• Develop test cases and stimulus to increase functional coverage for DRAM and emerging memory architectures.
• Collaborate with cross‑geo teams (US, Japan) to create new verification flows.
• Maintain test benches, test vectors and run regression suites for coverage analysis.

Required profile

• Minimum 3 years of relevant experience; Master’s degree preferred.
• Strong communication, debugging abilities and teamwork skills.
• Experience with analog/mixed‑signal circuits and full‑chip verification activities.
• Familiarity with AI‑enabled tools and automation frameworks is a plus.
• Fundamental knowledge of CMOS and FinFET technologies.
• Previous work in memory domains (HBM, DRAM, SRAM) is advantageous.

Required skills

• FastSpice tools (Primesim, FineSim, SpectreFx).
• Analog SPICE simulation tools (Hspice, Virtuoso).
• Verification platforms (Xcelium, SimVision, WaveView).
• SystemVerilog and UVM‑based verification.
• Scripting in Perl and Python.
• Static timing analysis concepts.
• Understanding of CMOS and FinFET processes.
• Knowledge of DRAM critical timing concepts.