RTL Integration (Frontend) Engineer

About the role

EdgeCortix is looking for a motivated Front‑End Design Engineer to own the integration of its Dynamic Neural Accelerator® IP and third‑party IPs into complex SoC architectures. You will work on cutting‑edge AI‑hardware co‑design, contributing to high‑performance, energy‑efficient edge computing solutions.

Key responsibilities

• Own IP integration into ASSP/SOC, including EdgeCortix DNA and third‑party IPs.
• Run RTL rule checkers (Lint), CDC, RDC, LEC and ensure design correctness.
• Develop verification infrastructure with VIPs, memory models, and monitors.
• Perform ECO flows, elaboration checks, and physical synthesis.
• Automate integration flows and generate design constraints with analysis.

Required profile

• 4‑7 years of RTL integration, front‑end design checks, STA and PPA experience.
• Knowledge of Chisel environments and IP protocols such as PCIe/UCIe, AXI, DDR, NIC.
• Experience with RISC‑V and FPGA integration is a plus.
• Prior CPU/Memory/Bus integration at subsystem level and strong understanding of physical design flows.

Required skills

• Verilog, C/C++, Tcl, Ruby, Perl, Python, Makefile.
• RTL design, synthesis, static timing analysis, power analysis.
• Gate‑level netlists, physical design flows, Cadence tool chain.
• PCIe, UCIe, AXI, DDR, NIC, RISC‑V, FPGA, Chisel, formal equivalence.

What we offer

• Highly competitive salary.
• Flexible work time.
• Top‑tier employee benefits.