Principal Physical Design Engineer (RTL-to-GDSII)

About the role

EnCharge AI seeks a Principal Physical Design Engineer who thrives on complexity and rejects the "black box" approach to EDA tools. You will transform raw RTL into world‑class silicon on sub‑5nm nodes, eliminating bottlenecks and building a scalable, predictable path to GDSII.

Key responsibilities

• Lead full‑flow implementation of massive, high‑speed blocks/SoCs from synthesis through sign‑off using the Cadence Digital Suite.
• Push the theoretical limits of the PDK and tools, optimizing library cells, metal stacks, and tool engines for maximum PPA.
• Build and refine a "push‑button" execution methodology that is robust, repeatable, and minimizes manual iterations.
• Collaborate early with RTL, architecture, and DFT teams to influence design decisions and align physical constraints with architecture.
• Identify and eliminate execution bottlenecks, creating automated solutions to bypass runtime, convergence, or tool limitations.

Required profile

• 14+ years of physical design experience with multiple sub‑5nm tape‑outs.
• Holistic thinker who can solve timing by adjusting floorplan or RTL/architecture.
• Strong influence and rapport building with front‑end, foundry, and EDA vendors.
• First‑principles critical thinker who challenges vendor best practices when needed.
• Mentor who elevates the technical competence of the entire PD team.

Required skills

• Cadence Innovus, Tempus, Joules, Pegasus, Voltus.
• Tcl and Python scripting for custom flow wrappers and data‑mining.
• Static Timing Analysis (STA), Physical Verification (PV), Power Integrity (PI) and ECO methodology.
• Deep knowledge of sub‑5nm physics: EUV constraints, multi‑patterning, FinFET, IR/EM challenges.