Physical Design Lead – AI SoC Development

About the role

Edgecortix is seeking a senior Physical Design Lead to own the end‑to‑end physical implementation of AI‑focused System‑on‑Chips, chiplets and hardened IP blocks. You will drive Power, Performance and Area (PPA) optimization from RTL through GDSII, providing technical leadership to both internal teams and external implementation partners.

Key responsibilities

• Lead RTL‑to‑GDSII implementation for AI SoCs, ensuring successful tape‑out with optimal PPA.
• Guide the Physical Design team and external partners, overseeing synthesis, floorplanning, placement, CTS, routing, STA and sign‑off across multiple PVT corners.
• Develop and refine design methodologies, automation flows and implementation constraints (SDC, TCL).
• Own power planning, UPF implementation, power‑grid generation, IR‑drop and EM analysis.
• Collaborate with Architecture, RTL, Verification, DFT and Product Engineering to provide continuous feedback and improve system‑level PPA.

Required profile

• Bachelor's degree in Electrical or Computer Engineering (Master's preferred).
• 8+ years of physical design experience on complex SoCs, with 10‑15+ years preferred.
• Proven track record of tape‑outs using Synopsys and/or Cadence tools.
• Experience with advanced nodes (12nm and below) and external design service partners.

Required skills

• Synopsys and Cadence EDA tool suites.
• STA, synthesis, floorplanning, CTS, placement & routing, MMMC, DVFS, UPF.
• Power planning, IR‑drop, EM analysis, DRC/LVS sign‑off.
• Scripting in TCL, Python and Shell.
• Timing closure, ECO implementation and constraint management.

What we offer

• Highly competitive salary and stock options (as applicable).
• Flexible work time.
• Top‑tier employee benefits.