Physical Design Engineer – AI Acceleration SoCs

About the role

We are looking for an experienced Physical Design Engineer to join EdgeCortix’s AI acceleration SoC and chiplet projects. You will drive synthesis, timing closure and design optimisation, collaborating closely with RTL, architecture and external implementation partners.

Key responsibilities

• Maintain RTL‑to‑GDSII flow, focusing on synthesis, static timing analysis and design closure.
• Define floorplans, block partitioning and placement strategies for hierarchical designs.
• Coordinate with external P&R vendors, review outputs and ensure quality.
• Analyse timing paths across PVT corners, develop constraints (SDC, TCL) and run equivalence checks.
• Implement low‑power strategies using UPF and review power‑grid, IR‑drop and EM sign‑off reports.

Required profile

• Bachelor’s degree in Electrical or Computer Engineering.
• 5+ years of physical design experience on SoCs, with strong synthesis and timing expertise.
• Hands‑on experience with advanced technology nodes (12 nm and below).

Required skills

• STA and synthesis tools such as PrimeTime, Design Compiler, Genus.
• Scripting in TCL, Python and Shell.
• Floorplanning, placement, clock‑tree implementation and congestion analysis.
• Low‑power flow using UPF, DVFS and MMMC.
• ECO handling and sign‑off checks (LVS, DRC, IR‑drop, EM).

What we offer

• Highly competitive salary and stock options.
• Flexible work time and top‑tier employee benefits.