Lead DFT Engineer – Edge Computing

About the role

EnCharge AI is seeking a seasoned Lead Design‑for‑Test (DFT) Engineer to drive the testing strategy for its next‑generation edge‑computing silicon. You will own the end‑to‑end DFT architecture, ensuring chips are manufacturable, reliable, and power‑efficient for remote data‑center deployments.

Key responsibilities

• Define and implement the full DFT architecture for complex SoCs, including hierarchical DFT, scan compression, boundary scan and MBIST.
• Develop edge‑specific reliability strategies such as In‑System Test (IST) and power‑on self‑test (POST) to guarantee chip health in remote environments.
• Oversee scan insertion, ATPG (stuck‑at, transition, path‑delay) and memory/logic BIST flows.
• Collaborate with design, physical‑design and yield teams to maximise test coverage while minimising area, power and timing impact.
• Lead post‑silicon bring‑up and debug on automated test equipment, root‑causing failures and optimising test time.

Required profile

• 12+ years of DFT experience, with at least 2 years in a lead or principal role.
• Proven track record in advanced FinFET nodes (7 nm, 5 nm or below) and low‑power, multi‑voltage designs.

Required skills

• Expertise with industry DFT tools such as Synopsys TestMAX, Siemens/Mentor Tessent or Cadence Modus.
• Deep knowledge of MBIST with repair, SCAN, IJTAG (IEEE 1687) and boundary‑scan (IEEE 1149.1/6).
• Strong experience in ATPG, scan insertion, and timing analysis.