IC Verification Engineer

About the role

The IC Verification Engineer is responsible for developing functional models, test benches, and verification environments for analog and digital IPs, ensuring comprehensive validation of ASIC designs. The role involves defining integration concepts, specifying test requirements, and collaborating with cross‑functional teams to deliver high‑quality verification on schedule.

Key responsibilities

• Collect and evaluate IC test and validation requirements in cooperation with other discipline developers.
• Define and apply verification strategies and test‑bench architectures using SystemVerilog, UVM, and C‑driven environments.
• Develop detailed verification plans, environments, and test sequences aligned with circuit specifications.
• Communicate technical details with ASIC suppliers and approve simulation/design results against system requirements.
• Plan project schedules, track validation progress, and maintain development documentation while applying configuration and change management.

Required profile

• 6–12 years of experience in ASIC/IC verification.
• Master’s degree in Electrical Engineering, Microelectronics, VLSI design or equivalent; Bachelor’s with advanced VLSI coursework is also acceptable.
• Knowledge of organizational standard processes such as risk and project management.
• Familiarity with functional safety standards (ISO 26262) and system security/privacy (UNECE WP29).

Required skills

• SystemVerilog
• UVM methodology
• C programming for test‑bench development
• ASIC verification flow and test automation tools