Design Verification Engineer (AI Hardware)

About the role

Edgecortix is looking for a talented Verification Engineer to join its Artificial Intelligence Hardware team. You will work closely with design and architecture groups to build and optimise verification environments for next‑generation AI SoCs.

Key responsibilities

• Collaborate with the design architecture team on IP, performance and SoC verification.
• Develop verification infrastructure including VIPs, memory models and monitors.
• Write configurable SystemVerilog/UVM testbenches and automate testbench execution.
• Create and maintain SystemVerilog assertions and functional coverage.
• Perform ASIC power estimation and power‑aware verification.
• Run gate‑level simulations, emulations and generate result reports.

Required profile

• 6‑7 years of functional verification experience using SystemVerilog/UVM.
• Strong knowledge of assertion‑based, metric‑driven and coverage‑driven verification techniques.
• Proven ability to build full verification infrastructure from scratch.
• Experience with high‑speed bus protocols such as AXI4, PCIe, DDR, UCIe or Ethernet.
• Hands‑on experience with emulator‑based verification and gate‑level simulation.
• Excellent debugging skills for RTL and testbenches.

Required skills

• SystemVerilog
• UVM
• AXI4, PCIe, DDR, UCIe, Ethernet protocols
• Emulator‑based verification
• Gate‑level simulation and delay modelling
• Perl, Python scripting
• Continuous Integration tools (Jenkins, GitLab CI, CircleCI)

What we offer

• Highly competitive salary and stock options.
• Flexible work time.
• Top‑tier employee benefits.