VLSI Engineer (Level 3) – Verification & Design

About the role

We are looking for a Level‑3 VLSI Engineer to develop and verify complex VLSI systems for our clients. The role involves defining architecture, layout, and implementation while ensuring high‑quality verification and timely delivery.

Key responsibilities

• Define functionality, architecture, layout and implementation of VLSI modules/IPs.
• Create verification environments and test benches using Universal Verification Methodology (UVM).
• Develop and code test cases, execute regression suites, and debug failures.
• Perform functional coverage analysis and document results in SharePoint or JIRA.
• Provide customer support, generate status reports and maintain design change repositories.
• Write scripts to automate verification tasks and assist in system upgrades.
• Ensure compliance with project plans, industry standards and documentation requirements.

Required profile

• 3–5 years of experience in VLSI design and verification.
• Strong understanding of module/IP architecture and verification flow.
• Ability to produce clear documentation and communicate progress to clients.
• Experience working in a team‑oriented, deadline‑driven environment.

Required skills

• VLSI Board Design
• Universal Verification Methodology (UVM)
• Test‑bench development and test‑case coding
• Scripting for automation (e.g., Python, Tcl)
• SharePoint and JIRA for documentation and issue tracking