Senior System-on-Chip Design Engineer

About the role

Edgecortix is building a new Design Center in Hyderabad to develop high‑efficiency AI silicon. As a Senior System‑on‑Chip (SoC) Design Engineer you will lead RTL design, integration and verification activities for cutting‑edge AI accelerator IPs.

Key responsibilities

• Drive SOC RTL design, integration and quality checks, collaborating with DFT, verification and physical design teams.
• Own PPA, design constraints, lint, CDC and power‑aware analyses to deliver production‑grade silicon.
• Mentor junior engineers and foster strong cross‑functional collaboration across global teams.
• Influence technical strategy, contribute to architecture discussions and drive innovation through patents or new methodologies.

Required profile

• 10+ years in the semiconductor industry with experience leading SoC design and verification teams.
• Strong background in wireless standards, signal processing and high‑speed interfaces (DDR, PCIe, ENET, UCIe).
• Hands‑on experience with ARM, RISC‑V or PowerPC cores and low‑power design techniques.

Required skills

• ASIC implementation: synthesis, static timing analysis (STA), ECO, power intent, lint, CDC/RDC analysis.
• RTL development and verification, DFT, floor‑planning, place‑and‑route (P&R) and chiplet/SiP integration.
• Expertise in memory subsystem architecture, AXI/APB interfaces and power‑management.
• Proficiency with high‑speed peripherals (DDR, PCIe, ENET, UCIe) and common interfaces (QSPI, I2C, USB).
• Knowledge of neural accelerators, CPUs, clocking, boot modes and security architectures.

What we offer

• Competitive compensation package.
• Comprehensive paid time off, vacations and sick leaves.