Principal Physical Verification Engineer

About the role

We are looking for a Principal Physical Verification Engineer to lead full‑chip and block‑level PV sign‑off for our VLSI designs. You will work closely with physical design, PDK, CAD and tape‑out teams to ensure silicon meets foundry and reliability requirements.

Key responsibilities

• Perform Design Rule Check (DRC), Layout Versus Schematic (LVS), Electrical Rule Check (ERC), antenna, density and reliability checks for block and full‑chip designs.
• Drive sign‑off closure by identifying, debugging and resolving PV violations efficiently.
• Develop and maintain runsets, decks and automation flows using industry‑standard EDA tools.
• Analyze foundry decks and PDK updates to ensure process compliance.
• Lead tape‑out readiness reviews and deliver high‑quality databases.
• Manage hierarchical verification and regression testing.
• Interface with foundry and EDA vendors to resolve tool or deck issues.
• Mentor junior engineers and review their work.

Required profile

• Strong analytical and problem‑solving abilities with a focus on quality and timelines.
• Effective communication across cross‑functional teams.
• Ownership mindset and ability to work independently while guiding team members.

Required skills

• Design Rule Check (DRC)
• Layout Versus Schematic (LVS)
• Electrical Rule Check (ERC)
• Antenna, density and reliability verification
• Runset and deck development
• Automation flow creation
• Foundry deck and PDK analysis
• Hierarchical verification
• Regression management
• Experience with industry‑standard EDA tools