Lead Physical Design Engineer

About the role

We are looking for a highly skilled Lead Physical Design Engineer to lead RTL synthesis and static timing analysis for next‑generation SoC designs. The role requires deep expertise in timing closure for complex semiconductor products.

Key responsibilities

• Lead RTL synthesis and comprehensive STA at block, subsystem, and SoC levels.
• Develop, integrate, and maintain SDC timing constraints across design hierarchies.
• Identify, debug, and resolve timing violations, including setup, hold, OCV, AOCV, EMIR, and crosstalk checks.
• Collaborate with design, DFT, physical design, and verification teams to achieve timing closure.
• Mentor junior engineers and drive continuous improvement of STA methodologies.

Required profile

• Approximately 10 years of experience in RTL synthesis and STA for semiconductor designs.
• Strong problem‑solving skills with the ability to debug complex timing issues.
• Proven ability to work cross‑functionally and meet project deadlines.

Required skills

• RTL synthesis
• Static Timing Analysis (STA)
• SDC constraint development
• OCV, AOCV, EMIR, and crosstalk analysis
• Scripting for STA automation