Lead Full Chip EM/IR Analysis Engineer

About the role

The focus of this role is to build, execute, and sign‑off on power and EM/IR (EMIR) closure for IP and full‑chip SOCs. The engineer will lead EMIR analysis across tile, partition, subsystem and SOC levels on a given technology node.

Key responsibilities

• Drive power and EMIR closure for design blocks and full‑chip integration, aligning analysis phases with product development milestones.
• Analyze EMIR violations, propose implementation choices, and ensure compliance with sign‑off limits provided by the SIPI team.
• Define EMIR sign‑off strategy, review floorplan, clocking and bus structures for IR hotspots, and coordinate bump allocation and power‑rail alignment with integration teams.
• Maintain and improve the EMIR flow, conduct run reviews and debug sessions with block owners, PD and integration teams.

Required profile

• Passion for complex processor architecture, digital design and verification, with strong analytical and problem‑solving skills.
• Excellent communication and teamwork abilities, able to collaborate with engineers across multiple sites and time zones.
• Minimum 7‑10 years of experience in ASIC physical design and sign‑off, with a track record as a technical lead on full‑chip projects.

Required skills

• EMIR analysis and power closure, IR‑drop and electromigration sign‑off.
• Physical‑design tools: Synthesis, ICC2 / Fusion Compiler, floorplan and clock‑tree analysis.
• Sign‑off tools: Redhawk_Sc, Voltas, PT‑PX, PrimeTime.
• Scripting languages: Shell, Python, Perl, TCL, UNIX.
• Familiarity with DFx, scan architecture and AI‑assisted problem solving.