Validation & Verification Engineer

About the role

The Validation & Verification Engineer will ensure technical feasibility and performance of power‑system concepts through systematic testing and analysis. Working within the Validation & Verification team, you will support laboratory setups, field commissioning and new product introduction for HVDC and substation equipment.

Key responsibilities

• Participate in RTDS lab setup and maintain the test environment.
• Independently execute Factory Site Tests (FST) and Factory Acceptance Tests (FAT) on shift schedule.
• Develop and maintain activity plans aligned with project milestones.
• Create test cases based on software requirements and document results.
• Communicate failure details to engineering functions and support debugging.
• Travel to global sites for static and dynamic commissioning activities.
• Review test outcomes, report status and suggest improvements.
• Collaborate with Continuous Improvement leaders to enhance processes.

Required profile

• Engineering degree (or equivalent) with focus on power systems or power electronics.
• Minimum 5 years of experience in HVDC or related power‑system validation.
• Strong English communication skills.
• Ability to work both in office and on international sites.
• Proactive learner and team player.

Required skills

• MATCAD, PSCAD, PSS/E, MATLAB/Simulink, EMTP‑RV, DIgSILENT.
• Knowledge of IEC 61850, IEC 62351, IEC 12207, IEEE 15288, IEC 25010, IEC 27032, NERC/CIP standards.
• Understanding of HVDC control systems and substation equipment (circuit breaker, isolator, CT, PT, transformer).
• Familiarity with PLC, DCS, SCADA, HMI, digital and analog signal interfaces.
• Proficiency with Microsoft Office (Word, Excel) and Microsoft Project.