Senior PCIe Verification Engineer

About the role

We are seeking an experienced Senior PCIe Verification Engineer to join our SoC Verification team. The role involves developing robust verification environments, driving verification closure, and ensuring first‑pass silicon success for PCIe‑based subsystems.

Key responsibilities

• Develop and execute comprehensive verification plans for PCIe IPs, subsystems, and SoC integration.
• Build reusable SystemVerilog/UVM verification environments from scratch.
• Create constrained‑random and directed test scenarios covering LTSSM, link training, configuration space, and PHY interactions.
• Verify advanced PCIe features such as MSI‑X, AER, ASPM, SR‑IOV, and power‑management.
• Develop functional coverage models, assertions, scoreboards, and protocol checkers, and drive verification closure.
• Support gate‑level simulations, regression execution, and post‑silicon bring‑up activities.

Required profile

• 6–12 years of functional verification experience using SystemVerilog and UVM.
• Strong expertise in PCI Express (Gen4/Gen5/Gen6) verification and hands‑on use of PCIe Verification IP.
• Hands‑on experience with 2–3 successful SoC tape‑outs and PCIe integration at the SoC level.
• Solid understanding of PCIe architecture, protocol layers and error handling.
• Experience verifying DMA‑based PCIe designs and AXI‑to‑PCIe bridge architectures.

Required skills

• SystemVerilog
• UVM
• PCI Express (Gen4/Gen5/Gen6)
• PCIe Verification IP
• AXI4 protocol
• DMA concepts
• SystemVerilog Assertions (SVA)
• Constrained‑random and coverage‑driven verification
• Gate‑level and timing‑aware simulation
• RTL and protocol debugging

What we offer

• Highly competitive salary and stock options
• Flex work time
• Top‑tier employee benefits