Senior ASIC Implementation Engineer

About the role

We are looking for a Senior ASIC Implementation Engineer to join Edgecortix’s new Design Center in Hyderabad. The role involves leading ASIC implementation activities such as synthesis, timing closure, power intent definition, and validation while collaborating with cross‑disciplinary teams.

Key responsibilities

• Perform logic and physical synthesis using advanced optimization techniques to generate gate‑level netlists optimized for timing, area and power.
• Debug timing, area and congestion issues in physical implementation and work with RTL and physical design teams to resolve them.
• Estimate power at RTL and gate level, develop power intent specifications (UPF) and identify reduction opportunities.
• Run formal verification, lint, CDC and RDC checks, create waivers and resolve equivalency failures.
• Develop timing constraints for synthesis and PrimeTime‑STA, and execute complex ECO flows.
• Participate in physical design activities from floor‑planning through place‑and‑route.

Required profile

• Bachelor’s degree in Science, Engineering or a related field.
• At least 4 years of hands‑on ASIC design, verification or implementation experience.
• Strong knowledge of industry‑standard synthesis tools and STA fundamentals.
• Proficiency in scripting languages such as Python, Perl or Tcl.

Required skills

• Logic and physical synthesis, timing closure, and congestion debugging.
• Power intent definition (UPF) and power analysis.
• Formal verification, lint, CDC and RDC checking.
• Conformal ECO flow and large ECO implementation.
• Physical design tasks including floor‑planning, place‑and‑route and power planning.

What we offer

• Competitive compensation package.
• Comprehensive paid time off, vacation and sick leave.
• Opportunity to work at a well‑funded fabless AI semiconductor startup shaping edge AI hardware.